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U3900BM
Programmable Telephone Audio Processor
Description
The programmable telephone audio processor U3900BM is a linear integrated circuit for use in feature phones, answering machines, fax machines and cordless phones. It contains the speech circuit, tone-ringer interface with DC/DC converter, sidetone equivalent and ear-protection rectifiers. The circuit is line-powered and contains all components necessary for signal amplification and adaptation to the line. The U3900BM can also be supplied via an external power supply. An integrated voice switch with loudspeaker amplifier enables hands-free or loudhearing operation. With an anti-feedback function, acoustical feedback during loudhearing can be reduced significantly. The generated supply voltage is suitable for a wide range of peripheral circuits.
Features
D D D D D D D D D D D
Speech circuit with anti-clipping Tone ringer interface with DC/DC converter Speaker amplifier with anti-distortion Power-supply management, regulated, unregulated and a special supply for electret microphone Voice switch CLID + SCWID DTMF generator Switch matrix Line current information Fully programmable Watchdog
Benefits
D Savings of one piezoelectric transducer D Complete system integration of analog signal
processing on one chip
D Very few external components D Highly integrated solution D Extremely versatile due to full programmability
Applications
Feature phone, answering machine, fax machine, speaker phone, base station of cordless phone
Speech circuit
Voice switch
Audio amplifier
Clock Data Reset
DTMF
Serial bus
MCU
Tone ringer
Class
14602
Ordering Information
Extended Type Number U3900BM-AFN U3900BM-AFNG3 Package SSO44 SSO44 Remarks Taped and reeled
Rev. A2, 25-Aug-98
1 (34)
Target Specification
U3900BM
Pin Description
SAO1 SAO2 GND VB ES VMPS SENSE VL IND
1 2 3 4 5 6 7 8 9 44 43 42 41 40 39 38 37 36 35 34 33 32
TSACL MIC2 MIC1 VMIC MIC3 TXACL RECO2 RECO1 TLDR INLDR INLDT TLDT HFTX
Pin 11 12 13 14 15 16 17 18
Symbol ADIN CLI2 CLI1 VRING IMPA COSC CLID input 2 CLID input 1
Function Input of A/D converter
Input for ringer supply Input for adjusting the ringer input impedance 70-kHz oscillator for ringing power converter
SWOUT Output for driving the external switching transistor VMP Regulated output voltage for supplying the microcontroller (typ. 3.3 V/ 6 mA in speech mode) Interrupt line for serial bus Clock input for serial bus Data line for serial bus Input for 3.58-MHz oscillator Reset output for the microcontroller Input for sidetone network Input for sidetone network Output for connecting the sidetone network Input for playback signal of answering machine
RECIN 10 ADIN 11 CLI2 12 CLI1 13 VRING 14 IMPA 15 COSC 16 SWOUT 17 VMP 18 INT 19 BCL 20 BDA 21 OSCIN 22
14761
19 20 21 22 23 24 25 26 27 28 29 30
INT BCL BDA OSCIN RESET STC STRC STO AMPB
OSCOUT Clock output for the microcontroller
31 CEAR 30 CMIC 29 AMREC 28 AMPB 27 STO 26 STRC 25 STC 24 RESET 23 OSCOUT
AMREC Output for recording signal of answering machine CMIC CEAR HFTX TLDT INLDT INLDR TLDR RECO1 RECO2 TXACL MIC3 VMIC MIC1 Input for cordless telephone Output for cordless telephone Output for transmit-level detector in intercom mode Time constant of transmit-level detector Input of transmit-level detector Input of receive-level detector Time constant of receive-level detector Positive output of the receive amplifier, also used for sidetone network Negative output of the receive amplifier Time-constant adjustment for transmit anticlipping Input of hands-free microphone Reference node for microphone amplifier, supply for electret microphone Inverting input of symmetrical microphone amplifier with high common-mode rejection ratio Non-inverting input of symmetrical microphone amplifier with high common-mode rejection ratio Time-constant for speaker amplifier anticlipping
31 32 33 34 35 36 37 38 39 40 41 42
Figure 1. Pinning
Pin 1 2 3 4 5 6 7 8 9 Symbol SAO1 SAO2 GND VB ES VMPS SENSE VL IND Function Positive output of speaker amplifier (single ended and push-pull operation) Negative output of speaker amplifier (push-pull only) Ground, reference point for DC- and AC signals Unstabilized supply voltage Input for external supply indication Unregulated supply voltage for the microcontroller (via series regulator to VMP) Input for sensing the available line current Positive supply-voltage input to the device in speech mode The internal equivalent inductance of the circuit is proportional to the value of the capacitor at this pin. A resistor connected to ground may be used to adjust the DC mask. Receive amplifier input
43
MIC2
44
TSACL
10
RECIN
2 (34)
Rev. A2, 25-Aug-98
Target Specification
U3900BM
Table of Contents
1 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 CLID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 Carrier Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.3 Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.4 Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.5 Data Recovery and Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.6 CLID: Logical Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.7 Carrier Detect, Bandpass Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.8 Special Carrier Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 SCWID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Guard Time, Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4 Up Guard Time, Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5 Early Guard Time, Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.6 Down Guard Time, Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.7 Wetting Pulse Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.8 SCWID: Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.9 CAS Detect Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Line Interface and Supply-Voltage Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Supply Structure of the Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ringing Power Converter (RPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Ringing Frequency Detector (RFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Output Divider Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTMF Dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Melody - Confidence Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acoustic Feedback Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sidetone System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 5 5 5 5 5 6 6 6 6 6 7 7 7 7 8 8 8 9 9 10 10 12 12 12 13 13 13 13 14 14 18 18 20 21 22 24 26 26 26 26 33
3 4 5 6 7 8 9 10 11 12 13 14
15
Rev. A2, 25-Aug-98
3 (34)
Target Specification
1
U3900BM
4 (34)
39 42 43 40 V MIC
AGATX MICRO AGARX TXA
VL
Block Diagram
25
26
10
27
8
7
9
41 6
TXACL STBAL
Power supply
18 4 3 11 17
Target Specification
Rev. A2, 25-Aug-98
30 32 28
Offset canceler
DTMF/ melody Filter
Offset canceler MUX ADC
Figure 2. Block diagram
Ringing power converter
16 14 15 V RING
AMPB
CMIC
LRX
DTMF
MIC LIDET VMP RFDO
Switch matrix
AMREC CEAR EPO RXLS LTX
29 31 37
AGC REG POR Filters 13 RA DIV. SACL AFS control SA 1 2 35 36 33 34 BIDIR serial bus 20 21 19
1/8/16/32
TIP
38 44
CLID
12 RING
OSC.
3.58 MHz
22
23 5
24
RECO1
TXOUT
V MP
mC
14604
U3900BM
2 Class Function
a capture window (see the tables next page), and avoid a false detection. With the use of SCD bit the carrier detect function is improved, because after a normal carrier detection (NCD), a part (10 bits) of the channel seizure is taken in count before alerting the microprocessor. Note: When the CPE is off hook (SCWID mode) the CO sends FSK data without channel seizure. The mark signal = 80 bits 10 at 1200 bauds (1300 Hz continuously during 67 ms). For this case a selected bandpass 1000 Hz to 1700 Hz could be very useful for the carrier detect ... After the interrupt due to the carrier detect the microprocessor can change the bandpass frequencies according to the FSK band. The U3900BM includes a class function Calling Line IDentification (CLID) for on-hook and Spontaneous Call Waiting IDentifier (SCWID) for off-hook status.
2.1
CLID
CLID is designed to demodulate CCITT V23 and BELL 202 (1200 bauds FSK asynchronous data) and is compatible with both formats without external intervention. It fulfils the CS B14-10W requirements. The main feature of this part is to provide, for the user, information about the caller before answering the call. The information is a DATA message sent from the Central Office (CO) to the CPE during the silent interval, and after the first ringing burst.
2.1.1
Description
On the receive side, the received signal coming from CLI1 and CLI2 first goes to an antialiasing filter after the differential op-amp. The next section is a bandpass filter composed of an FSK filter composed of a fifth order high-pass followed by a third order low-pass filter. The low-pass and high-pass cut-off frequencies are about 300 Hz and 3400 Hz respectively.
D The normal carrier detect guard time is 26.4 ms. D The improved carrier detect guard time is 34.7 ms. D The carrier lost guard time is 8.8 ms, in all the cases.
2.1.3 Demodulator
This part is enabled with the carrier detect signal. The reference signal is at 1700 Hz, (the same frequency for BELL 202 and V23). All the incoming signals are compared to this value to make a digital square wave frequency varying in frequency and in phase as a function of the input frequencies.
2.1.2
Carrier Detect
The carrier detect provides an indication (to the microprocessor with an interrupt request) of the presence of a signal in the FSK band. It detects a sufficient amplitude signal at the output of the FSK bandpass filter. Note that signals such as speech or DTMF tones also lie in the FSK frequency band and the carrier detect may be activated by these signals. The signals will be demodulated and presented as DATA. To avoid false DATA detection, a command bit is used to disable the demodulator when no FSK signal is expected. Four bits are provided to improve carrier detection [CD_CD <3..0>]. With these bits it is possible to select
2.1.4
Clock Recovery
The process starts at the first low-level bit received from the demodulator. After that the CLOCK is generated for the 10 serial bits (1 bit start, 8 bits data, 1 bit stop).When all the data are received DATA READY is generated. This signal loads the serial data in a parallel buffer. DATA READY provides an indication (to the microprocessor with an interrupt request) of the presence data byte available.
Rev. A2, 25-Aug-98
5 (34)
Target Specification
U3900BM
2.1.5 Data Recovery and Buffer
is generated, the INT pin will become active, and data ready interrupt bit is set in the status register (bit 3). The received data is available in the CLID DATA register. The incoming serial data are stored and sent to the SSB each 10 bits (1 start bit, 8 data, 1 stop bit ). When after a start bit 8 data bits and a stop bit are received, an interrupt
DATA
Start
D0
D1
D2
D3
D4
D5
D6
D7
Stop
INT pin
14605
Figure 3. Interrupt treatment for SLID DATA register
2.1.6
CLID: Logical Part
Command bits CD_CD < 3...0 > from serial bus Command bit SCD from serial bus NCD FSK signal
CD
Carrier detect
Serial data
Data recovery and buffer
Clock
DATA
DR
Data ready
Demodulator
Clock recovery
From/to demodulator analog filter Figure 4. Block diagram for CLID logical part
14606
2.1.7 Carrier Detect, Bandpass Frequencies High Frequencies Low Frequencies
CD_CD<0> 0 1 0 1 CD_CD<1> 0 0 1 1 Value 290 Hz 515 Hz 770 Hz 1000 Hz CD_CD<2> 0 1 0 1 CD_CD<3> 0 0 1 1 Value 3400 Hz 3100 Hz 2665 Hz 1700 Hz
6 (34)
Rev. A2, 25-Aug-98
Target Specification
U3900BM
2.1.8
If SCD = 0 If SCD = 1
Special Carrier Detect
Detect guard time = 26.4 ms Detect guard time = 34.7 ms (26.4 ms + 10 bits of the channel seizure)
Channel seizure: 010101... SCD = 0 SCD = 1 Carrier detect (Interrupt)
26.4 ms 8.3 ms 8.8 ms
14077
FSK signal
Mark: 1111...
Clid Data Carrier lost
Figure 5. Timing diagram for carrier detect in CLID mode
2.2
SCWID
Mark: 1111... Clid Data Carrier lost ncd (SCWID)
26.4 ms 8.8 ms
14078
FSK signal Carrier detect (Interrupt)
CAS detector should also be immune to imitation from near and far end speech. Note that the term "near end" refers to the end of the telephone connection receiving the caller ID service, "far end" refers to the other end of the connection, the Central Office (CO). There are two aspects of speech immunity: talk-off and talk-down. Talk-off is the condition where signals are falsely detected because of imitation by speech or music. An imitation can be caused from the far end or the near end. Talk-down is the condition where signals are missed because of interference from speech or music. A CAS can be talked down only from the near end because the far end has already been muted by the CO.
Figure 6. Timing diagram for carrier detect in SCWID mode
The Spontaneous Call Waiting IDentifier (SCWID) part is designed to meet:
D The Bellcore "Customer Premises Equipment
Alerting Signal (CAS)": TR-NWT-000030 SR-TSV-002476 specifications. SIN227 & SIN242 specifications. &
D The British Telecom "Idle State Tone Alert Signal": D The European Telecommunication Standard: ETS300
778-1 & ETS300 778-2 specifications.
2.2.2
Description
2.2.1
Overview
SCWID is a feature that allows a subscriber who is already engaged in a telephone call to receive caller ID information about an incoming call. The European Telecommunication Standard specifies Dual-Tone Alerting Signal (DT-AS) for off-line data transmission (on-hook) and on-line data transmission (off-hook). The British Telecom caller ID uses a Idle State Tone Alert Signal in on-hook mode. Bellcore specifies a Dual-Tone Alert Signal called CPE Alerting Signal (CAS) for use in off-hook data transmission. Bellcore states that the CPE should be able to detect the CAS in the presence of near end speech. The Rev. A2, 25-Aug-98
The SCWID part is a complete dual-tone receiver designed to detect the two frequencies 2750 Hz and 2130 Hz dedicated for this alerting function. An output interrupt is provided to the microprocessor when detecting the alert signal. This device part provides all necessary filtering without any external component. The on-chip filtering provides excellent signal-to-noise performance. The dual-tone alert signal is divided into a high and a low bandpass switched capacitor filters:
D The high alert filter is a 2750 Hz bandpass design,
with a notch placed at 2130 Hz for low frequency rejection.
D The low alert filter is a 2130 Hz bandpass design, with
a notch placed at 2750 Hz for high frequency rejection. 7 (34)
Target Specification
U3900BM
The filter outputs are smoothed and then limited by highgain comparators which have hysteresis to reduce sensitivity to unwanted low-level signals, jitter and noise. The outputs of the comparators are square-wave signals. The two resulting rectangular waves are applied to the digital circuitry where a counting algorithm measures and averages their periods. This averaging prevents dual-tone SCWID simulation by extraneous signals such as voice. The averaging algorithm has been optimized to provide excellent immunity to "talk-off" and tolerance to the presence of interfering frequencies (third tones) and noise. When both digital circuitries simultaneously detect a valid tone (2130 Hz and 2750 Hz), the signal applied at the guard-time block goes high. Should the alert tone signal be lost, the input signal at the guard-time block will go low.
2.2.4
Up Guard Time, Description
The up guard time circuitry prevents false detection from speech or music (talk-off). The input signal (both 2130 Hz and 2750 Hz) must be continuously high for a duration depending on the 2 programmable bits UGT0 and UGT1. DGT0 0 1 0 1 DGT1 0 0 1 1 UGT Value 20 ms 25 ms 30 ms 35 ms
If a drop occurs at any time before the selected value, the detection system is cleared. Nevertheless, there is the possibility to improve such a system using early guard time circuitry.
2.2.5
Early Guard Time, Description
2.2.3
Guard Time, Overview
The early guard time system, when enabled, helps the up guard time to detect a CAS signal even if there are drops in it. But there are conditions before validating such a polluted signal. The input signal (both 2130 Hz and 2750 Hz) must be continuously high for duration depending on the 2 programmable bits EGT0 and EGT1. EGT0 0 1 0 1 EGT1 0 0 1 1 EGT Value Disabled 8.5 ms 10.3 ms 13.7 ms
To prevent false detection due to talk-off effects and to detect real CAS signals even with drops, a guard-time system is necessary. A guard-time system improves the detection performance and verifies that the duration of a valid signal is sufficient before alerting the microprocessor with an interrupt. It rejects detection of insufficient duration (up guard time) and mask dropouts (down guard time). There are nine bits for controlling the guard-time block:
D 2 bits, EGT0 and EGT1, for controlling the early
guard time
After that, the input signal is filtered and a drop can occur without clearing the system if it is not too long . The maximum time value depends on the command filter bit FFD. FFD Filter Value (Maximum Drop Duration) 2 ms 4 ms
D 2 bits, UGT0 and UGT1, for controlling the up guard
time
D 2 bits, DGT0 and DGT1, for controlling the down
guard time
0 1
If there are too many drops, the system is cleared. The count of drops admitted depends on the command count bit FDC. FDC 0 1 Count Value (Maximum Drop Count) 4 3
D 1 bit, FFD, for controlling the width filter D 1 bit, FDC, for controlling the drops count D 1 bit, WP, for enabling the wetting pulse function
One bit is dedicated for enabling the SCWID part. 8 (34)
The early guard time with filter and count drops allow a good compromise to achieve talk-off and talk-down immunity. Rev. A2, 25-Aug-98
Target Specification
U3900BM
2.2.6 Down Guard Time, Description 2.2.7 Wetting Pulse Function
The down guard time circuitry prevents drops from speech or music (talk-down). The input signal (both 2130 Hz and 2750 Hz) must be continuously low for a duration depending on the 2 programmable bits DGT0 and DGT1. The early guard time is used like for up guard time, but the drop counter is not activated. * Note: The Idle State is an electrical condition into which the TE (when connected to the network) is placed such that it draws minimum current and does not activate the exchange. DGT0 0 1 0 1 DGT1 0 0 1 1 DGT Value 15 ms 17 ms 18 ms 19 ms British Telecom states that the TE is required to apply a DC wetting pulse and an AC load 205 ms after the end of the alerting signal (the Idle State* Tone Alert Signal); the duration of the wetting pulse is 151 ms; the TE shall rise to a minimum of 25 mA and maintain that current for a total time of not less than 5 ms. OCTEL3 provides a 15-ms counter (which starts at the end of the alerting signal delayed by the down guard time value) to help the microprocessor to fulfil this requirement. The signals at the output of the guard time system are sent to the SSB-INTERRUPT treatment. An interrupt occurs at each edge of the OUT SCWID detector. When the wetting pulse is enabled (CDE8. mode UK = 1), an interrupt is sent to the microprocessor 15 ms after the falling edge of the WP detector.
Idle state tone alert signal duration: 100 10 ms frequencies: 2130 Hz + 2750 Hz
IN SCWID detector Choice of 4 UGT values Up guard time OUT SCWID detector OUT WP detector Choice of 4 DGT values Down guard time
Interrupt to the P
15 ms
Interrupt to the P WETTING PULSE (Under P control) 20 5 ms
Interrupt to the P
15 1 ms
Current that TE shall draw
Not less than 25 mA
Not less than 5 ms
14607
Figure 7. Alert detection timing diagram with wetting pulse
Rev. A2, 25-Aug-98
9 (34)
Target Specification
U3900BM
2.2.8 SCWID: Overview
CLASS signal 2130 Hz Analog filter Alert signal low-frequency logic part
EGT UGT DGT FC Command bits CDE < 0...8 > from serial bus
To interrupt system Wetting pulse W pulse
Time guard
2750 Hz Analog filter Alert signal high-frequency logic part To CLID FSK filter Figure 8. Alert detection
Alert
14608
General information: All the control bits provided for the SCWID function can be modified at any time with the microprocessor.
2.2.9
CAS Detect Process
Typical application: The incoming signal from the CO is not polluted with speech or music. (The feature early guard time is not used)
CAS signal duration: 80 5 ms frequencies: 2130 Hz + 2750 Hz
IN SCWID detector
Choice of 4 UGT values Up guard time
OUT SCWID detector
Choice of 4 DGT values Down guard time
Interrupt to the P
Interrupt to the P
14609
Figure 9. Timing diagram of standard alert detection
If any drop in the CAS signal occurs before the end of the UGT specified value, then the time counter restarts and the OUT SCWID detector remains low.
If any spike in the blank signal occurs before the end of the DGT specified value, then the time counter restarts and the OUT SCWID detector remains high.
10 (34)
Rev. A2, 25-Aug-98
Target Specification
U3900BM
CAS Detect Process (continued)
Improved process: To prevent false detection from speech and music by the far and the near end (talk-off), and to detect the incoming CAS signal from the CO, polluted with speech or music by the near end (talk-down), a new feature is used: the early and up guard time.
CAS signal duration: 80 5 ms frequencies: 2130 Hz + 2750 Hz mixed with speech and music frequencies Values permitted for drops after a successful early guard time
IN SCWID detector
3 Drops had no effect (FDD = 4 ms, FDC = 4)
Drops
In signal
Restart Early guard time Up guard time Interrupt to the P Choice of 4 UGT values
14610
OUT SCWID detector
Choice of 3 EGT values
Figure 10. Timing diagram for early and up guard time
Note: In the case above, the EGT counter restarts 3 times. After a sucessful 10.3-ms EGT, 3 drops occured but without any effect because the duration and the number is less than the maximum permitted.
CAS signal duration: 80 5 ms frequencies: 2130 Hz + 2750 Hz mixed with speech and music frequencies Filter values permitted for spikes after a successful early guard time
IN SCWID detector
Spikes in signal
mixed with speech and music frequencies
5 Spikes had no effect (FDD = 4 ms) Restart Early guard time Down guard time
OUT SCWID detector
Choice of 3 EGT values
Choice of 4 DGT values
Interrupt to the P
14611
Figure 11. Timing diagram of early and down guard time
Note: In the case above, the EGT counter restarts 3 times. After a sucessful 13.7-ms EGT, 5 spikes occured but without any effect because the duration is less than the maximum permitted.
Rev. A2, 25-Aug-98
11 (34)
Target Specification
U3900BM
3 DC Line Interface and Supply-Voltage Generation
For line voltages below 2 V, the switches remain in quiescent state as shown in the diagram. 2. When the chip is in power-down mode (Bit LOMAKE), e.g., during pulse dialing, all internal blocks are disabled via the serial bus, except the oscillator. In this condition, the voltage regulators and their internal bandgap are the only active blocks. 3. During ringing, the supply for the system is fed into VB via the Ringing Power Converter (RPC). Normally, the speaker amplifier in single-ended mode is used for ringing. The frequency for the melody is generated by the DTMF/Melody generator. 4. In an answering machine, the chip is powered by an external supply via Pin VB. The answering machine connections could be directly put to U3900BM. The answering machine is connected to the Pin AMREC. For the output AMREC, an AGC function is selectable via the serial bus. The output of the answering machine will be connected to the Pin AMPB, which is directly connected to the switching matrix, and thus enables the signal to be switched to every desired output.
The DC line interface consists of an electronic inductance and a dual-port output stage which charges the capacitors at VMPS and VB. The value of the equivalent inductance is given by: L=2 RSENSE CIND (RDC R30) / (RDC + R30)
The U3900BM contains two identical series regulators which provide a supply voltage VMP of 3.3 V suitable for a microprocessor. In speech mode, both regulators are active because VMPS and VB are charged simultaneously by the DC-line interface. The output current is 6 mA. The capacitor at VMPS is used to provide the microcomputer with sufficient power during long line interruptions. Thus, long flash pulses can be bridged or an LCD display can be turned on for more than 2 seconds after going on-hook. When the system is in ringing mode, VB is charged by the on-chip ringing power converter. In this mode, only one regulator is used to supply VMP with maximum 3 mA.
3.1
Supply Structure of the Chip
VL RSENSE 10 C 1 F IND R + - R 300 k V 220F
14573
As main benefit of the U3900BM is the easy implementation of various applications due to the flexible system structure of the chip. Possible applications:
5.5 V
VMPS 470F
- + + - 3.3 V VMP 47 F VB
D Group listening phone D Hands-free phone D Phones which feature ringing with the built-in speaker
amplifier
5.5 V
D Answering machine with external supply
Figure 12. Supply generator
The special supply topology for the various functional blocks is illustrated in figure 11. There are four major supply states: 1. 2. 3. 4. Speech condition Power down (pulse dialing) Ringing External supply
4
Ringing Power Converter (RPC)
1. In speech condition, the system is supplied by the line current. If the LIDET-block detects a line voltage above approximately 2 V, the internal signal VLON is activated. This is detected via serial bus, all necessary the blocks have to be switched on via the serial bus.
The RPC transforms the input power at VRING (high voltage/ low current) into an equivalent output power at VB (low voltage/ high current) which is capable of driving the low-ohmic loudspeaker. The input impedance at VRING is adjustable from 3 kW to 12 kW by RIMPA (ZRING = RIMPA / 100) and the efficiency of the stepdown converter is approximately 65%.
12 (34)
Rev. A2, 25-Aug-98
Target Specification
U3900BM
4.1 Ringing Frequency Detector (RFD)
6
Serial Bus Interface
The U3900BM provides an output signal for the microcontroller. This output signal is always double the value of the input signal (ringing frequency). It is generated by a current comparator with hysteresis. The levels for the on-threshold are programmable in 16 steps and the off-level is fixed. Every change of the comparator output generates a high level at the interrupt output INT. The information can then be read out by means of a serial bus with either a normal or a fast read mode. The block RFD is always enabled.
The circuit is controlled by an external microcontroller through the serial bus. The serial bus is a bi-directional system consisting of a one-directional clock line (BCL) which is always driven by the microcontroller, and a bi-directional data-signal line. It is driven by the microcontroller as well as from the U3900BM (see figure 12). The serial bus requires external pull-up resistors as only open-collector transistors (Pin BDA) are integrated. WRITE: The data is a 12-bit word:
AAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAAAAA
5 Clock Output Divider Adjustment
The Pin OSCOUT is a clock output which is derived from the crystal oscillator of the ceramic resonator. It can be used to drive a microcontroller or another remote component and thereby reduces the number of crystals required. The oscillator frequency can be divided by 1, 8, 16, 32. During power-on reset, the divider will be reset to 1 until it is changed by setting the serial bus.
RINGTH[0:3] min. 0 max. 15 step
VRING 7V 22 V 1V
A0 - A3: address of the destination register (0 to 15) D0 - D7: content of the register The data line must be stable when the clock is high. Data must be shifted serially. After 12 clock periods, the write indication is sent. Then, the transfer to the destination register is (internally) generated by a strobe signal transition of the data line when the clock is high (see figure 13). READ: There is a normal and a fast-read cycle. In the normal read cycle, the microcontroller sends a 4-bit address followed by the read indicator, then an 8-bit word is read out. The U3900BM drives the data line (see figure 14). The fast read cycle is indicated by a strobe signal. With the following two clocks the U3900BM reads out the status bits RFDO and LIDET which indicate that a ringing signal or a line signal is present (see figure 15).
AAAAAA A A AAAAAAAAAAAAAAAA AAAAAAAAAAA A AAAAAA A A AAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A AAAAAAAAAAA A A
6.1 Bus Timing BDA
twSTA tr tf
CLK[0:1] 0 1 2 3
Divider 1 8 16 32
Frequency 3.58 MHz 447 kHz 224 kHz 112 kHz
thSTA
BCL
Sf Sr thSTA tL thDAT tH tsSTA thDAT tsSTOP Sf
Sf = Strobe falling, SR = Strobe rising
Figure 13. Bus timing
14793
Rev. A2, 25-Aug-98
13 (34)
Target Specification
U3900BM
7 DTMF Dialing
0 1 2 3 The DTMF generator sends a multi-frequency signal through the matrix to the line. The signal is the result of the sum of two frequencies and is internally filtered. The frequencies are chosen from a low and a high frequency group. The circuit conforms to the CEPT recommendation concerning DTMF option (rec. T/CF 46-03). Two different levels for the low level group and two different preemphasis (2.5 dB and 3.5 dB) can be chosen by means of the serial bus.
AAAA A AA A A A AAAAAAAAAAAAAAAA AA A AA A A AAA AAAA A AA A A AAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAA AA A AA A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AA A AA A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAA AA A AA A A AA AAAA A AA A A AAAAAAAAAAAAAAAA AA A AA A A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AA AA A AAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AA AAAA AAAAAAAA AAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AA AAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AA A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAA AA A AA A A AAAA A AA A A AAAAAAAAAAAAAAAA AA AA A AA A A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AA A AA A A A A AA A A AAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAA A AA A A AAAAAAAAAAAAAAAA AA A AA A A AA A AA A A A A AA A A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAA A AA A A AAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAAAA
7.1
Melody - Confidence Tone Generation
Melody/confidence tone frequencies are given in the table below.
The frequencies are provided at the DTMF input of the switch matrix. A sinus wave, a square wave or a pulsed wave can be selected by the serial bus. Square signal means output is half of frequency cycle high and half low, so duty cycle of 50% square wave or 50% for pulsed signal. 0 1 2 3 4 5 6 7 DTMFM[0:2] 000 001 010 011 100 101 110 111 DTMF generator OFF Confidence tone melody on (sinus) Ringer melody (pulse) Ringer melody (square signal) DTMF(high level) DTMF(low level)
0 1 2 3
DTMFF[0:1] in DTMF Mode 00 01 10 11
Frequency
Error / %
697 770 852 941
-0.007 -0.156 0.032 0.316
14 (34)
Target Specification
AAAAA A A A AAAAAAAAAAAAAAAA AAA AAAAA A A A AAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAA AAA AA AAAAAAAAAAAAAAAA AAAAAAAAAAAA AA
1209 1336 1477 1633 -0.110 0.123 -0.020 -0.182 DTMFF4 in DTMF mode Preemphasis Selection 0 2.5 dB 1 3.5 dB
DTMFF [0:4] 0 00000 1 00001 2 00010 3 00011 4 00100 5 00101 6 00110 7 00111 8 01000 9 01001 10 01010 11 01011 12 01100 13 01101 14AAA 01110 15 01111 16 10000 17 10001 18 10010 19 10011 20 10100 21 10101 22 10110 23 10111 24 11000 25 11001 26 11010 27 11011 28 11100 29 11101 30 11110 31 11111 f Hz 440.0 466.2 493.9 523.2 554.4 587.3 622.3 659.3 698.5 740.0 784.0 830.0 880.0 932.3 987.8 1046.5 1108.7 1174.7 1244.5 1318.5 1396.9 1480.0 1568.0 1661.2 1760.0 1864.6 1975.5 2093.0 2217.5 2349.3 2663.3 2983.0 ToneName a1 b1 h1 c2 des2 d2 es2 e2 f2 ges2 g2 as2 a2 b2 h2 c3 des3 d3 es3 e3 f3 ges3 g3 as3 a3 b3 h3 c4 des4 d4 Error/% DTMF Key 1 4 7 * 2 5 8 0 3 6 9 # A B C D 1 4 7 * 2 5 8 0 3 6 9 # A B C D -0.008 697 1209 -0.016 770 1209 -0.003 852 1209 0.014 941 1209 0.018 697 1336 -0.023 770 1336 -0.129 852 1336 0.106 941 1336 -0.216 697 1477 -0.222 770 1477 0.126 852 1477 -0.169 941 1477 0.288 697 1633 -0.014 770 1633 -0.004AAA 852 1633 -0.335 941 1633 -0.355 697 1209 -0.023 770 1209 -0.129 852 1209 0.106 941 1209 -0.214 697 1336 -0.222 770 1336 0.126 852 1336 -0.241 941 1336 -0.302 697 1477 -0.014 770 1477 0.665 852 1477 0.367 941 1477 0.387 697 1633 0.771 770 1633 --- 852 1633 --- 941 1633
DTMFF[2:3] in DTMF Mode 00 01 10 11
Frequency
Error / %
Rev. A2, 25-Aug-98
U3900BM
Write cycle
CLOCK
DATA
D7
D6
D5
D4
D3
D2
D1
D0
A3
A2
A1
A0 R/W=0 Strobe fromP
Data fromP
14574
Figure 14. Write cycle
Normal read cycle
CLOCK
DATA
A3
A2
A1
A0
R/W=1 Strobe fromP
D7
D6
D5
D4
D3
D2
D1
D0
14794
Data fromP
Data from U3900BM
Figure 15. Normal read cycle
Fast read cycle
CLOCK
DATA Strobe from P
D7=IZC D6=IVE
Data from U3900BM
14795
Figure 16. Fast read cycle
Rev. A2, 25-Aug-98
15 (34)
Target Specification
U3900BM
Table 1. Names and functions of the serial bus registers Register Group No Name R0 Enables R0B0 ENRING R0B1 ERX R0B2 ETX R0B3 ENVM R0B4 ENMIC R0B5 ENSTBAL R0B6 MUTE R0B7 ENRLT R1 Enables R1B0 ENSACL R1B1 ENSA R1B2 ENSAO R1B3 ENAM R1B4 ENCT R1B5 ANAMAGC R1B6 ENCLID R1B7 ENSCWID R2 Matrix R2B0 I1O1 R2B1 I1O2 R2B2 I1O3 R2B3 I1O4 R2B4 I1O5 R2B5 I2O1 R2B6 I2O2 R2B7 I2O3 R3 Matrix R3B0 I2O4 R3B1 I2O5 R3B2 I3O1 R3B3 I3O2 R3B4 I3O3 R3B5 I3O4 R3B6 I3O5 R3B7 I4O1 R4 Matrix R4B0 I4O2 R4B1 I4O3 R4B2 I4O4 R4B3 I4O5 R4B4 I5O1 R4B5 I5O2 R4B6 I5O3 R4B7 I5O4 R5 Matrix R5B0 I5O5 AGATX R5B1 AGATX0 MICLIM R5B2 AGATX1 R5B3 AGATX2 R5B4 MICHF R5B5 DBM5 R5B6 MIC0 R5B7 MIC1 Description Enable ringer Enable receive part Enable transmit part Enable VM generator Enable microphone Enable sidetone balancing Muting earpiece amplifier Enable POR low threshold Enable anti-clipping for speaker amplifier Enable speaker amplifier and AFS Enable output stage speaker amplifier Enable answering machine connections Enable cordless telephone connections Enable answering machine AGC Enable CLID Enable SCWID Switch on MIC / LTX Switch on MIC / RXLS Switch on MIC / EPO Switch on MIC / CEAR Switch on MIC / AMREC Switch on DTMF / LTX Switch on DTMF / RXLS Switch on DTMF / EPO Switch on DTMF / CEAR Switch on DTMF / AMREC Switch on LRX / LTX Switch on LRX / RXLS Switch on LRX / EPO Switch on LRX / CEAR Switch on LRX / AMREC Switch on CMIC / LTX Switch on CMIC / RXLS Switch on CMIC / EPO Switch on CMIC / CEAR Switch on CMIC / AMREC Switch on AMPB / LTX Switch on AMPB / RXLS Switch on AMPB / EPO Switch on AMPB / CEAR Switch on AMPB / AMREC Gain transmit AGA LSB Gain transmit AGA Gain transmit AGA MSB Select RF-microphone input Max. transmit level for anti-clipping Gain microphone amplifier LSB Gain microphone amplifier MSB Status 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 (34)
Rev. A2, 25-Aug-98
Target Specification
U3900BM
Register R6 Group Sidetone No R6B0 R6B1 R6B2 R6B3 R6B4 R6B5 R6B6 R6B7 R7B0 R7B1 R7B2 R7B3 R7B4 R7B5 R7B6 R7B7 R8B0 R8B1 R8B2 R8B3 R8B4 R8B5 R8B6 R8B7 R9B0 R9B1 R9B2 R9B3 R9B4 R9B5 R9B6 R9B7 R10B0 R10B1 R10B2 R10B3 R10B4 R10B5 R10B6 R10B7 R11B0 R11B1 R11B2 R11B3 R11B4 R11B5 R11B6 R11B7 Name FOFFC DTAMAGC SL0 SL1 LF0 LF1 LF2 LF3 P0 P1 P2 P3 P4 AGARX0 AGARX1 AGARX2 EA0 EA1 EA2 EA3 EA4 IMPSEL LOMAKE SD AFS0 AFS1 AFS2 AFS3 AFS4 AFS5 AFSM ALT SA0 SA1 SA2 SA3 SA4 SE LSCUR0 LSCUR1 ADC0 ADC1 ADC2 ADC3 NWT SOC ADCR MSKIT Description Speed up offset canceller Decay time answering machiune AGC Slope adjustment for sidetone LSB Slope adjustment for sidetone MSB Low-frequency adjustment for sidetone LSB Low-frequency adjustment for sidetone Low-frequency adjustment for sidetone Low-frequency adjustment for sidetone MSB Pole adjustment for sidetone LSB Pole adjustment for sidetone Pole adjustment for sidetone Pole adjustment for sidetone Pole adjustment for sidetone MSB Gain receive AGC LSB Gain receive AGC Gain receive AGC MSB Gain earpiece amplifier LSB Gain earpiece amplifier Gain earpiece amplifier Gain earpiece amplifier Gain earpiece amplifier MSB Line-impedance selection (1 = 1 kW) Short circuit during pulse dialing Shut down AFS gain adjustment LSB AFS gain adjustment AFS gain adjustment AFS gain adjustment AFS gain adjustment AFS gain adjustment MSB AFS mode Antilarsen threshold Gain speaker amplifier LSB Gain speaker amplifier Gain speaker amplifier Gain speaker amplifier Gain speaker amplifier MSB Speaker amplifier single-ended mode Speaker amplifier charge-current adjustment LSB Speaker amplifier charge-current adjustment MSB Input selection ADC Input selection ADC Input selection ADC Input selection ADC Network tuning Start of ADC conversion Selection of ADC range Mask for interrupt bits Status 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R7
Sidetone AGARX
R8
EARA PS
R9
AFS
R10
SA
R11
ADC
Rev. A2, 25-Aug-98
17 (34)
Target Specification
U3900BM
Register R12 Group DTMF No R12B0 R12B1 R12B2 R12B3 R12B4 R12B5 R12B6 R12B7 R13B0 R13B1 R13B2 R13B3 R13B4 R13B5 R13B6 R13B7 R14B0 R14B1 R14B2 R14B3 R14B4 R14B5 R14B6 R14B7 R15B0 R15B1 R15B2 R15B3 R15B4 R15B5 R15B6 R15B7 Name DTMFF0 DTMFF1 DTMFF2 DTMFF3 DTMFF4 DTMFM0 DTMFM1 DTMFM2 CLK0 CLK1 RTH0 RTH1 RTH2 RTH3 TME0 TME1 TME2 TME3 Description DTMF frequency selection DTMF frequency selection DTMF frequency selection DTMF frequency selection DTMF frequency selection Generator mode selection Generator mode selection Generator mode selection Selection clock frequency for mC Selection clock frequency for mC Ringer threshold adjustment LSB Ringer threshold adjustment Ringer threshold adjustment Ringer threshold adjustment MSB Test mode enable (low active) Test mode enable (high active) Test mode enable (high active) Test mode enable (low active) Status 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R13
CLK RTH TM
R14
TM CLID
ENRXCL GSCWID WP UGT0 UGT1/SCD DGT0/CDLF0 DGT1/CDLF1 EGT0/CDHF0 EGT1/CDHF1 FDD FDC
Selection of internal CLID input signals Gain adjustment of SCWID behind sidetone Wetting pulse SCWID up guard time SCWID up guard time/ CLIB special carier detect SCWID down guard time/ CLID LF carrier detect SCWID down guard time/ CLID LF carrier detect SCWID early guard time/ CLID HF carrier detect SCWID early guard time/ CLID HF carrier detect Filter drop duration Filter drops count
R15
CLID
8
Power-on Reset
9
Watchdog Function
To avoid undefined states of the system when it is powered on, an internal reset clears the internal registers. The system (U3900BM + microcontroller) is woken up by any of the following conditions: VMP > 2.75 V and VB > 2.45 V and line voltage (VL) or ringer (VRING) or external supply (ES) The power-down of the circuit is caused by a shut-down sent by the serial bus (SD = 1), low-voltage reset or by the watchdog function (see figures 16, 17 and 18).
To avoid the system operating the microcontroller in a wrong condition, the cicuit provides a watchdog function. The watchdog has to be retriggered every second by triggering the serial bus (sending information to the IC or other remoted components at the serial bus). If there has been no bus transmission for more than one second the watchdog iniates a reset.
18 (34)
Rev. A2, 25-Aug-98
Target Specification
U3900BM
Line LID IVDD OSCOUT ton
VMP Reset trt - ton = 4.5 ms ton = start-up oscillator Figure 17. Power-on reset (line)
trt
14585
VRING VB IVDD VMP OSCOUT Reset ton trt Figure 18. Power-on reset (ringing)
14586
Line LID VMP IVDD LVR
IVDD Reset OSCOUT
14612
Figure 19. Power-on reset if low voltage reset enabled
Rev. A2, 25-Aug-98
19 (34)
Target Specification
U3900BM
10 Acoustic Feedback Suppression
Acoustical feedback from the loudspeaker to the microphone may cause instability of the system. The U3900BM has a very efficient feedback-suppression circuit which uses a modified voice switch topology. Figure 20 shows the basic system configuration. Two attenuators (TXA and SAI) reduce the critical loop gain via the serial bus either in the transmit or in the receive path. The sliding control in block AFS control (figure 19) determines whether the TX or the RX signal has to be attenuated. The overall loop gain remains constant under all operating conditions. Selection of the active channel is made by a comparison of the logarithmically compressed TX- and RX- envelope curve. Figure 19 shows the AFS control. The system configuration for group listening, which is implemented in the U3900BM, is illustrated in figure 21. TXA and SAI represent the two attenuators, whereas the logarithmic envelope detectors are shown in a simplified way (operational amplifiers with two diodes). Receive and transmit signals are first processed by logarithmic rectifiers in order to produce the envelopes of the speech at TLDT and RLDT. After amplification a TLDT + - TLDR BUS IAFS decision is made by the differential pair as to which direction should be transmitted. The attenuation of the controlled amplifiers TXA and SAI is determined by the emitter current IAFS which is bus programmable.
IDTXA
IDSAI
14613
Figure 20. AFS control
TXA MICRO LOG
AFS control
Line
LOG SA SAI
14591
Figure 21. Basic system configurations
20 (34)
Rev. A2, 25-Aug-98
Target Specification
U3900BM
TLDT TXA SAI
TX
INLDT
+ - TX INLDR BUS I AFS BUS I GSA
TLDR
14614
Figure 22. System configuration for group listening
11 Analog-to-Digital Converter (ADC)
The circuit is a 7-bit successive approximation analogto-digital converter in switched capacitor technique. An internal bandgap circuit generates a 1.25-V reference voltage which is the equivalent of 1 MSB. 1 LSB = 19.5 mV. The possible input voltage at ADIN is 0 to 2.48 V. The ADC needs an SOC (Start Of Conversion) signal. In the `High' phase of the SOC signal, the ADC is reset. 50 ms after the beginning of the `Low' phase of the SOC signal the ADC generates an EOC (End Of Conversion) signal which indicates that the conversion is finished. The rising edge of EOC generates an interrupt at the INT output. The result can be read out by the serial bus. Voltages higher than 2.48 V have to be divided. The signal which is connected to the ADC is determined by 5 bits ADC0, ADC1, ADC2, ADC3 and NWT. TLDR/TLDT measuring is possible relative to a preceding reference measurement. The current range of IL can be doubled by ADCR. If ADCR is `High', S has the value 0.5, otherwise S = 1. The source impedance at ADIN must be lower than 250 kW. Accuracy: 1 LSB 3%
SOC 50 s EOC Figure 23. Timing of ADC
14594
IL
20mV/(1mA
S)
SOC
ADIN 0.4 VB 0.4 VMPS 0.75 VMP 8 8 (TLDR-REF) (TLDT-REF) 0.4 0.4 0.4 0.4 SAO1 OFF1 OFF2 OFF3 EOC
14595
MSB BIT5 BIT4
ADC
BIT3 BIT2 BIT1 LSB
Figure 24. ADC input selection
Rev. A2, 25-Aug-98
21 (34)
Target Specification
U3900BM
Table 2. Input selection AD converter
AAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAA A A A A
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OFF IL ADIN external VB VMPS VMP TLDR TLDT Free SAO1 Offcan1 Offcan2 Offcan3 Free Free Free I1 = S 127 mA D / 127 V2 = 2.5 V D / 127 (max. 2.5 V) V3 = (2.5 V / 0.4) D / 127 V4 = (2.5 V / 0.4) D / 127 V5 = (2.5 V / 0.75) D / 127 V6 = 1/8 (Vp - Ref) D / 127 V7 = 1/8 (Vp - Ref) D / 127 V4 = (2.5 V / 0.4) D / 127 TEMIC internal use TEMIC internal use TEMIC internal use D = measured digital word (0 < = D < = 127) S = programmable gain 0.5 or 1 Vp = peak value of the measured signal
ADC[0:3] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Value
12 Switch Matrix
The switch matrix has 5 inputs and 5 outputs. Every pair of input and output can be connected. The inputs and outputs used must be enabled. If 2 or more inputs are switched to an output, the sum of the inputs is available at the output. The inputs MIC and LRX have offset cancellers with a 3-dB corner frequency of 270 Hz. AMPB and CMIC have a 60-kW input impedance. The TXO output has a digitally-programmable gain stage with a gain of 2, 3 to 9 dB depending on AGATX0 (LSB), AGATX1, AGATX2 (MSB) and a first-order low-pass filter with 0.5 dB damping at 3300 Hz and 3 dB damping at 9450 Hz. The outputs RXLS, EPO and CEAR have a gain of 0 dB. If a switch is open, the path has a damping of more than 60 dB.
AMPB CMIC LRX DTMF MIC Offset canceller I5 I4 I3 I2 Offset canceller I1
Lowpass O5 O4 O3 O2 O1 2 ... 9 dB LTX AMREC EPO RXLS AGATX0 AGATX1 AGATX2 TXO -10 dB STO Figure 25. Diagram of switch matrix
14079
AGC
AGCI
22 (34)
Rev. A2, 25-Aug-98
Target Specification
AAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A A A
Table 3. Table of bits and corresponding switches
Rev. A2, 25-Aug-98 R5 R4 R3 R2 Register Matrix Matrix Matrix Matrix Group R5B0 R4B7 R4B6 R4B5 R4B4 R4B3 R4B2 R4B1 R4B0 R3B7 R3B6 R3B5 R3B4 R3B3 R3B2 R3B1 R3B0 R2B7 R2B6 R2B5 R2B4 R2B3 R2B2 R2B1 R2B0 No. I5O5 I5O4 I5O3 I5O2 I5O1 I4O5 I4O4 I4O3 I4O2 I4O1 I3O5 I3O4 I3O3 I3O2 I3O1 I2O5 I2O4 I2O3 I2O2 I2O1 I1O5 I1O4 I1O3 I1O2 I1O1 Name Switch on AMPB / AMREC Switch on AMPB / CEAR Switch on AMPB / EPO Switch on AMPB / RXLS Switch on AMPB / LTX Switch on CMIC / AMREC Switch on CMIC / CEAR Switch on CMIC / EPO Switch on CMIC / RXLS Switch on CMIC / LTX Switch on LRX / AMREC Switch on LRX / CEAR Switch on LRX / EPO Switch on LRX / RXLS Switch on LRX / LTX Switch on DTMF / AMREC Switch on DTMF / CEAR Switch on DTMF / EPO Switch on DTMF / RXLS Switch on DTMF / LTX Switch on MIC / AMREC Switch on MIC / CEAR Switch on MIC / EPO Switch on MIC / RXLS Switch on MIC / LTX Description
Target Specification
U3900BM
23 (34)
U3900BM
13 Sidetone System
The Sidetone Balancing (STB) has the task to reduce the crosstalk from LTX (microphone) to LRX (earpiece) in the frequency range of 0.3 to 3.4 kHz. The LTX signal is converted into a current in the MOD block. This current is transformed into a voltage signal (LINE) by the line impedance ZL. The LINE signal is fed into the summing amplifier DIFF1 via capacitor CK and attenuator AMP1. On the other side the LTX buffered by STOAMP drives an external low-pass filter (RST, CST). The external lowpass filter and the internal STB have the transfer function drawn in the STB box. The amplified STB-output signal drives the negative input of the summing block. If both signals at the DIFF1 block are equal in level and phase, we have a good suppression of the LTX signal. In this condition the frequency and phase response of the STB block will represent the frequency curve on line. In real live the line impedance ZL varies strongly for different users. To reach a good suppression with one application for all different line impendances, the STB function is programmable. The 3 programmable parameters are 1. LF (gain at low frequency). LF has 15 programming steps. LF(0) gives -2 dB gain, LF(15) gives 5.5 dB gain.
LF Step gain LF Step gain 0 -2 8 1.9 1 2 3 0.1 11 3.0 4 0.6 12 3.6 5 1.0 13 4.2 6 1.3 14 4.8 7 1.6 15 5.5 -1.3 -0.6 9 2.2 10 2.5
STO_DIFF(LF) = (-10 dB - 2 dB + 0.5 dB
LF + 9 dB)
LTX
2. P (the pole position of the lowpass). The P adjustment has 31 Steps. P(0) means the lowpass determined by the external application (RST, CST). The internally processed low-pass frequency is fixed by this equation. 1 1.122 P f(P) 2 p CST RST 3. SL (sidetone slope; the pole frequency of the highpass) The SL have 3 steps. SL(0) is a lower frequency of the highpass. SL(3) is a higher frequency of the highpass. With SL we can influence the suppression at high frequencies.
+
LTX
8dB
LINE CK ZL
LRX
0-7dB
+ DIFF1 -
STO_DIFF
MOD
-10dB
RECIN STO
AGARX
AMP1
-10dB
9dB
AMP2
STOAMP
Sidetone balancing
LF STRC
STO 8.2 k
g
P
CTO 33 nF SL STC
f
14579
LF
P
SL
Figure 26. Programmable sidetone supression circuit
24 (34)
Rev. A2, 25-Aug-98
Target Specification
U3900BM
< = 32 dB SE Offset canceler CHARLSC ENSA 200 k 100 k SAI - + ENSA V V B VB_REG M ENSA SACL 100 k ENSA EN [1:6] PROG_SAI V M EN V M - + 100 k 100 k V B 100 k - + V B V M 30 k 50 V B 100 k - + V B SAO1 47 F LSCUR [1:2] V 0 / 6 dB V CFN B M
SAO2
IDSAI ENSACL
ENSA Ron = 2
TSACL ENSA ENSAO SE
14593
Figure 27. Speaker amplifier
-10dB -3dB ... -10dB and 7dB (NWT)
Offset cancel
32dB -14.5dB
ST Sidetone balancing
7dB0dB and 20dB (NWT)
SAO1
6dB
Line
VL
Offset cancel
1dB steps
LRX
RXLS
1.5dB steps 26dB-3dB and -10dB (DTMF)
Loud- speaker SAO2 RECO1 Earpiece DTMF
< -40dBm/ -38dBm >
DTMF generator MIC1 Handset micro- phone MIC2 Handsfree micro- phone Cordless CMIC MIC3
0dB 6dB steps 0dB 30dB12dB 7dB
Filter
DTMF
< -24dBm/ -22dBm >
DTMF
EPO
1dB steps 9dB2dB
Switching matrix
Offset cancel
MIC LTX
RECO2
VL
8dB 1dB steps
TXA
1dB steps
Line
MOD
CEAR
0dB
AMPB
AMREC
0dB
Answering machine
0dB
AGCO
AGCI
0dB
AGC
AMPB
AMREC Answering machine
14620
Figure 28. Audio frequency signal management U3900BM
Rev. A2, 25-Aug-98
25 (34)
Target Specification
AAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A A AAA A A A A A A A AA A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A AA A A A A AA A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAA A A A A A A A AA A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A AA A A A A AA A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A AA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA
f = 1 kHz, 0 dBm = 775 mVrms, IVMIC = 0.3 mA, IMP = 3 mA, RDC = 1.3 M, Tamb = 25C, Zear = 68 nF + 100 , ZM = 68 nF, f = 3.58 MHz, all bits in reset condition, unless otherwise specified. Note 1)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA
14.1 Absolute Maximum Ratings 14.3 Electrical Characteristics 14.2 Thermal Resistance
Junction ambient Parameters Line current DC line voltage Maximum input current Junction temperature Ambient temperature Storage temperature Total power dissipation, Tamb = 60C Parameters SSO44 Symbol RthJA Symbol IL VL IRING Tj Tamb Tstg Ptot Value 140 12 15 125 -25 to +75 -55 to +150 0.9 Value 70 Unit K/W Unit mA V mA C C C W
14 Technical Data
U3900BM
IL = 2 mA 2.4 VL 4.6 5.4 IL = 14 mA 5.0 IL = 60 mA 7.5 8.8 10.0 IL = 100 mA 9.4 Transmission amplifier, IL = 14 mA, VMIC = 2 mVRMS, MICG[0:1] = 2, AGATX[0:2] = 7 ERX = ETX = ENMIC = ENSTBAL = I1O1 = I3O3 = 1, (GT = 48 dB) Transmit amplification MICG[0:1] = 2 GT 46 47 48 AGATX[0:2] = 7 Frequency response IL 14 mA, DGT -1 0 (see note 1) f = 3.4 kHz Gain change with IL = 14 to 100 mA DGT 0.5 current Gain deviation Tamb = -10 to +60C DGT 0.5 CMRR of microphone CMRR 60 80 amplifier Input resistance of Ri 50 MIC amplifier Input resistance of MICHF = 1 Ri 75 150 300 MIC3 amplifier Gain difference MICHF = 1 DGT 0.4 between MIC1, MIC2 to MIC3 Distortion at line IL 14 mA dt 2 VL = 700 mVrms
26 (34)
Parameters DC characteristics DC voltage drop-over circuit
Frequency response is due to internal filters
Test Conditions / Pins
Target Specification
Symbol Min. Typ. Max. Rev. A2, 25-Aug-98 Unit k k dB dB dB dB dB dB % V Fig.
AAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA A A A A AA A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAA A A A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAAAAA AAAAAAA A AA A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAA A A A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAA A A A A A A AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Electrical Characteristics (continued)
Receiving amplifier IL = 14 mA, VGEN = 300 mV, ERX = ETX = ENMIC = ENSTBAL = I1O1 = I3O3 = 1, SL[0:1] = 0, LF[0:3] = 1, P[0:4] = 31, AGARX[0:2] = 0 Adjustment range of Single ended, GR -25 11 receiving gain IL 14 mA, Mute = 1, EA[0:4] = 2 - 31 AGARX[0:2] = 0 - 7 Receiving amplificaDifferential tion AGARX[0:2] = 0 GR -1 0 1 EA[0:4] = 21 10 11 12 EA[0:4] = 31 Frequency response IL 14 mA, f = 3.4 kHz DGRF -1 0 Gain change with cur- IL = 14 to 100 mA DGR 0.5 rent Gain deviation Tamb = -10 to +60C DGR 0.5 Ear protection IL 14 mA, EP 3 differential VGEN = 11 Vrms MUTE suppression IL = 14 mA DGR 60 Output voltage d < 2% IL = 14 mA tbd. differential Zear = 68 nF + 100 EA[0:4] = 11 Maximum output Zear = 100 10 current d < 2% EA[0:4] = 31 Distortion at low operating current release time Gain at low operating current Anti-clipping: attack time Noise at line psophometrically weighted Parameters Maximum output voltage IL = 8 mA IMP = 1 mA RDC = 680 k VMIC = 0.5 mV IVMIC = 300 mA IL = 8 mA IMP = 1 mA RDC = 680 k VMIC = 5 mV IVMIC = 300 mA CTXA = 1 mF each 3 dB overdrive Test Conditions / Pins IL 19 mA, d < 5% VMIC = 10 mV CTXA = 1 F DBM5 = 0 DBM5 = 1, VMIC = 14 mV VMIC = 20 mV MICG[0:1] = 3 IL 14 mA MICG[0:1] = 2 AGATX[0:2] = 7 VLmax VMICOmax Symbol VLmax tr GT no dt ta Min. 1.3 46.5 3.8 Typ. 2.5 - 80 5.0 -5.2 0.5 16
Rev. A2, 25-Aug-98
Target Specification
U3900BM
Max. 3.7
49.5
- 72
6.2
5
dBmp
mAp
dBm dBm
Unit dBm
Vrms
dB Vrms
dB
dB dB dB dB
dB
ms dB
ms
%
27 (34) Fig.
AAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA A A AA A A A AA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
dBm dBm dBm dBm mW mW mW mA dB dB
AA A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAA A A A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A AA A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AA A AA A A A AAA A A A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A AA A A AA A A A AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Electrical Characteristics (continued)
U3900BM
AMPB RECO1/2 -16 EA[0:4] = 1 DTMF, IL = 14 mA, ETX = I201 = 1, AGATX[0:2] = 7, DTMFM[0:2] = 4, DTMFF[0:2] = 0 Max. level at line Sum level, 600 W, -5.1 -3.6 -2.1 DTMFM[0:2] = 5 DTMF level at line Sum level, 600 W, -7.6 -6.1 -4.6 (low gain) DTMFM[0:2] = 4 Preemphasis 600 W, DTMFF4 = 0 2 2.5 3 DTMFF4 = 1 3 3.5 4 Speaker amplifier, differential mode AMPB SAO1/2 ENSACL = ENSA = ENSAO = ENAM = I5O2 = 1, SA[0:4] = 0 Minimum line current No AC signal ILmin 8 for operation Gain from AMPB to VAMPB = 3 mV, IL = 15 mA, GSA 37 38 39 SAO SA[0:4] = 31 -8.5 SA[0:4] = 0 Adjustment step DSA[0:4] = -1 1.3 1.5 1.7 speaker amplifier Output power Load resistance: single ended RL = 50 , d < 5% VAMPB = 20 mV, SE = 1 PSA 3 7 IL = 15 mA PSA IL = 20 mA 20 Max. output power Load resistance: PSA 200 differential RL = 50 , d < 5% VAMPB = 20 mV, SE = 0 VB = 5 V
28 (34)
Adjustment step: ear-piece amplifier Adjustment step: AGARX Gain for DTMF signal
Distortion at low operating current
AC impedance
Parameters Receiving noise psophometrically weighted Sidetone suppression Output resistance Gain at low operating current (receive only)
Test Conditions / Pins IL = 14 mA Zear = 68 nF + 100 EA[0:4] = 21 Z = 600 Each output against GND IL = 5 mA, IMP = 1 mA IM = 300 mA VGEN = 200 mV RDC = 680 k, EA[0:4] = 21, ENMIC = ETX = I101 = 0 IMPH = 0 IMPH = 1 IL = 8 mA, IMP = 1 mA VGEN = 400 mV RDC = 680 k EA[0:4] = 21 AGARX[0:4] = 1
EA[0:4] = 1
Target Specification
Symbol Zimp Zimp dR Ro GR Min. 570 950 0.8 0.8 -2 20 600 1000 Typ. - 80 1 1 0 Max. - 77 640 1050 5 1.2 1.2 10 2 Rev. A2, 25-Aug-98 Unit dBmp dB dB dB dB dB %
W W
W
Fig.
AA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AA AA A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AA AA A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA A A A A AA A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AA A A A AA A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AA A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAA A A A A A A AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A A A A A AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AA A A A AA A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAA A A A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Electrical Characteristics (continued)
Gain change with DGSA current Gain change with IL = 15 mA f = 3.4 kHz DGSA -1 frequency Attack time of 20 dB over drive tr 5 anti-clipping Release time of tf 80 anti-clipping Charge current ENSAO = 0, SE = 1 ICHA -1.45 -1.2 Pin SAO2 LSCUR[0:1] = 3 Discharge current ENSAO = 0, SE = 0 IDIS 0.95 1.2 Pin SAO2 LSCUR[0:1] = 3 Adjustment step of ENSAO = 0, SE = 1 -480 -400 charge current DLSCUR[0:1] = 1 Adjustment step of ENSAO = 0, SE = 0 320 400 discharge current DLSCUR[0:1] = 1 Microphone amplifier, VB = 5 V, VMIC = 2 mV, VMIC3 = 2 mV, ENMIC = ENCT = I1O4 = 1, MICHF = 0 Gain MIC Amp.: MICG[0:1] = 0 18.4 19 MIC1/2 CEAR MICG[0:1] = 1 24.4 25 MICG[0:1] = 2 30.4 31 MICG[0:1] = 3 36.4 37 MIC3 CEAR MICHF = 1, MICG[0:1] = 3 36.4 37 Input suppression: MICG[0:1] = 3, MICHF = 0 60 MIC3 MIC1/2 MIC1/2 MIC3 MICHF = 1 60 Settling time FOFFC = 0 9 offset-cancellers, 5 t Settling time offsetFOFFC = 1 1.8 cancellers in speed-up mode, 5 t AGC for answering machine, AMPB AMREC, ENAM = I5O5 = 1 Nominal gain VAMPB = 5 mV -1 0 Max. output level VAMPB = 50 mV, d< 5% 160 200 Attack time 20 dB overdrive 2 Release time 100 Mute suppression Parameters Output noise (input AMPB open) psophometrically weighted Gain deviation IL = 15 mA Tamb = -10 to +60C IL = 15 mA, VL = 0 dBm, VAMPB = 4 mV, I5O2 = 0 IL = 15 to 100 mA Test Conditions / Pins IL > 15 mA Symbol VSAO
Rev. A2, 25-Aug-98
Target Specification
DGSA
nSA Min. 60 Typ.
U3900BM
-0.95
Max.
-320
19.6 25.6 31.6 37.6 37.6
1.45
1 240
480
240
2.4
1
1
12
0
mVpsoph
dB mVp ms ms
Unit
mA
mA
mA
mA
ms
dB dB ms
dB dB dB dB dB
ms
ms
dB
dB
dB dB
29 (34) Fig.
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A AA A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAA AAA AAAAAAAA AAAAAAA A A AA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA A A A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A AA A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAA A A A A A A A AA A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A A A A A A AA A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A AA A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A AA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Electrical Characteristics (continued)
U3900BM
Parameters Test Conditions / Pins Symbol Min. Typ. Max. Unit Switching matrix, VL = 0, VB = 5 V, ENCT =ENAM = I4O4 = I5O4 = 1, VAMPB = VCMIC = 1 Vrms Input impedance 50 60 70 k AMPB, CMIC Gain CMIC CEAR, -0.4 0 0.4 dB AMREC CEAR Max. input level 600 mV AMPB, CMIC Max. output level VB- VPP CEAR 600 mV Offset I4O4: 1 0 DVAMREC 30 mV Mute switching matrix I4O4 = 0 60 dB Power-on reset VL = 0, VMP = 3.3 V, VB = 5 V, U3900BM in power-down mode Power-on reset by VMP VB = 4 V, ES = 4 V, VMPon 2.65 2.75 2.85 V threshold, VL or rise VMP VRING or ES high Power-on reset by VB VMP = 3 V, ES = 3 V, VBon 2.85 2.95 3.05 V threshold, VL or VRING rise VB or ES high Low voltage interrupt VL = 0, VMP = 3.3 V, VB = 0 V VMP decreasing Decrease VMP until INT VLVI 2.5 2.6 2.7 V returns to high Power-off reset VL = 0, VMP = 3.3 V, VB = 0 V Low voltage reset Decrease VMP until RESET VLVR 2.35 2.45 2.55 V returns to low Difference voltage VLVI - VLVR 100 150 mV between low voltage interrupt and reset Logical part VMP = 3.3 V, VB = 5 V Output impedance at 0.5 1.0 k OSCOUT Pins BCL, Low level 0.2 VMP V 0.8 VMP BDA (input mode) High level V
30 (34)
-1 1 Input leakage current 0 < Vi < VMP Pins INT, Output low 220 310 400 BDA (output mode) (resistance to GND) AFS acoustic feedback suppression, IL = 14 mA, VGEN = 300 mV, ERX = ETX = ENMIC = ENSTBAL = I1O1 = I3O3 = 1, SL[0:1] = 0, LF[0:3] = 1, P[0:4] = 31, AGARX[0:2] = 0 Adjustment range of IL 15 mA 0 50 attenuation Attenuation of transmit IL 15 mA, IINLDT = 0 mA DGT 48 50 52 gain IINLDR = 10 mA Attenuation of speaker IL 15 mA, IINLDT = 10 mA GSA 48 50 52 amplifier IINLDR = 0 mA
Target Specification
Rev. A2, 25-Aug-98
mA
dB dB dB
Fig.
U3900BM
Electrical Characteristics (continued)
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3.3 3.5 5.7 4 V V V V 5.5 6.3 20 mW 6.5 7 7 V V V V 7.7 24 1.2 6 22 1 5 k V VDD 1.5 0.4 100 1 300 V V V kHz
Parameters Test Conditions / Pins Symbol Min. Supply voltages, VMIC = 25 mV, Tamb = - 10 to + 60C VMP IL = 14 mA, RDC = 680 kW VMP 3.1 IMP = 3 mA VMPS IL = 100 mA, RDC = inf., VMPS IMP = 0 mA VMIC IL 14 mA, RDC = 1.3 MW VMIC 1.5 IM = 700 A VB IB = +20 mA, IL = 0 mA VB VL = 100 mA Ringing power converter, IMP = 1 mA, IM = 0 RIMPA = 500 kW Maximum output VRING = 20.6 V, PSA power DTMFM[0:2] = 3 I2O2 = ENSA = ENSAO = SE = 1 Threshold VRING: high to low low to high 6.3 RINGTH [0:3] = 0 low to high 20 RINGTH [0:3] = 15 Adjustment steps DRINGTH = 1 0.8 threshold Input impedance VRING = 30 V 4 Z-diode voltage IRING = 25 mA VRINGmax 30.8 Serial bus BCL, BDA, AS, VMP = 3.3 V, RBDA = RBCL = RINT = 12 kW Input voltage BDA, BCL, ViBUS HIGH INT 3.0 LOW 0 Output voltage BDA Acknowledge LOW IBDA = 3 mA VO Clock frequency BCL fBCL Rise time BDA, BCL tr Fall time BDA, BCL tf Period of BCL HIGH HIGH tH 4.0 LOW LOW 4.7 tL Setup time Start condition tsSTA 4.7 Data 250 tsDAT Stop condition 4.7 tsSTOP Time space 1) 4.7 twSTA Hold time Start condition thSTA 4.0 DATA 0 thDAT
Typ.
Max.
Unit
Fig.
ms
ns
ms ms ms ms ms ms ms
ns
1)
This is a space of time where the bus must be free from data transmission and before a new transmission can be started
Rev. A2, 25-Aug-98
31 (34)
Target Specification
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Electrical Characteristics (continued)
U3900BM
32 (34) Band-limited random noise 300 to 3400 Hz. Present only when tone is present. Speech tolerance Speech level is in ASL (Active Speech Level). Over the CAS signal level range -16 dBm to -30 dBm per performance objectives stated in SR-TSV-002476 appendices A&B. Tone alert guard time and wetting pulse signal Early guard time - 1 Disabled -2 -3 -4 Up guard time -1 -2 -3 -4 Down guard time - 1 -2 -3 -4 Wetting pulse signal Delay after the Alert Signal delay falling edge Parameters Alert tone detection Low tone frequency High tone frequency Frequency deviation accept Frequency deviation reject Accept signal level per tone Reject signal level per tone Positive and Negative twist accept Noise tolerance Range within which tones are accepted Range within which tones are rejected Test Conditions / Pins Symbol SNR TONE wpd dgt ugt egt fl fh 0.75 37.78 Min. 3.5 - 8.3 10.1 13.4 19.5 24.5 29.5 34.5 17.5 19.5 21.5 24.5 14.8 tbd tbd 7 2130 2750 Typ. - 8.5 10.3 13.7 20 25 30 35 18 20 22 25 15 tbd 20 - 8.7 10.5 14.0 20.5 25.5 30.5 35.5 18.5 20.5 22.5 25.5 15.2 0.22 tbd tbd
Target Specification
-43.78 Max. Rev. A2, 25-Aug-98 dBm dBm dBm Unit ms ms ms ms Hz Hz % % dB dB Fig.
U3900BM
Electrical Characteristics (continued)
Parameters FSK detection Input signal power level 1) Reject signal level (threshold) 2) Input signal level 3) Reject signal level (threshold) 2) Transmission rate (CCITT V23 & BELL 202) Space frequency (CCITT V23) Mark frequency (CCITT V23) Space frequency (BELL 202) Mark frequency (BELL 202) Signal-to-noise ratio 1) 2) 3) Test Conditions / Pins On-HOOK mode On-HOOK mode Off-HOOK mode Off-HOOK mode Symbol Pifon Prjon Pifoff Prjoff Tr SfV MfV SfB MfB S/N fsk Min. -38 -44 -38 -44 1188 2079 1287 1178 1188 20 Typ. Max. -1.5 -1.5 1200 2100 1300 2200 1200 1212 2121 1313 2222 1212 dBm Unit dBm dBm dBm dBm baud Fig.
200 - 340 baud
Referenced to a 600 W termination at the CPE Tip and Ring interface. Input signal at Pins CLI1 and CLI2. Signal lower than -43.8 dBm is rejected. Referenced to a 600 W termination at the CPE Tip and Ring interface. With a maximum gain in the RX chain. Input signal at Pin VL.
15 Package Information
Package SSO44
Dimensions in mm
18.05 17.80 9.15 8.65 7.50 7.30
2.35 0.3 0.8 16.8 44 23 0.25 0.10
0.25 10.50 10.20
technical drawings according to DIN specifications 13040
1
22
Rev. A2, 25-Aug-98
33 (34)
Target Specification
U3900BM
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( ODSs). The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2831, Fax number: 49 ( 0 ) 7131 67 2423
34 (34)
Rev. A2, 25-Aug-98
Target Specification

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